Concurrent Assignment Errors: Understanding and Resolving ‘Concurrent Assignment to a Non Net is Not Permitted’

In digital design and Verilog programming, the concept of “concurrent assignment to a non-net is not permitted” is crucial. This rule means that you cannot assign values to variables of type reg or integer in a continuous assignment statement. Continuous assignments are only allowed for wire types, which represent connections between hardware elements. This distinction ensures that the design accurately reflects the intended hardware behavior, maintaining the integrity of the digital circuit.

Understanding Concurrent Assignment

In Verilog, concurrent assignment refers to the use of the assign statement to continuously drive a value onto a net. This means the assignment is always active and updates the net whenever the right-hand side (RHS) expression changes.

Concurrent assignment to a non-net is not permitted because only nets can represent physical connections in hardware. Variables like reg are used for storage and procedural assignments, which are evaluated sequentially within procedural blocks. Allowing concurrent assignments to variables would conflict with their intended use and could lead to unpredictable behavior in the hardware design.

Common Errors and Causes

Common errors related to the “concurrent assignment to a non-net is not permitted” in Verilog typically arise from the following issues:

1. Incorrect Data Type Declaration:

   • Cause: Assigning a value to a reg type in a continuous assignment.
   • Solution: Use wire for continuous assignments. Example:

     wire [7:0] P;
     assign P = A & B; // Correct
     

2. Misuse of reg in Combinational Logic:

   • Cause: Declaring outputs as reg in purely combinational modules.
   • Solution: Declare outputs as wire for combinational logic.

     module comb_logic(output wire [7:0] P, input [3:0] A, B);
     assign P = A + B; // Correct
     endmodule
     

3. Port Mapping Issues:

   • Cause: Using reg types for ports that are driven by continuous assignments.
   • Solution: Ensure ports driven by continuous assignments are declared as wire.

     module example(output wire P, input A, B);
     assign P = A & B; // Correct
     endmodule
     

4. Instantiation of Primitives:

   • Cause: Using reg types for signals connected to primitive gates.
   • Solution: Use wire types for signals connected to primitives.

     wire P;
     and (P, A, B); // Correct
     

These errors often stem from misunderstanding the distinction between reg and wire types in Verilog. Ensuring proper data type usage can prevent these issues.

Solutions and Best Practices

To avoid the “concurrent assignment to a non-net is not permitted” error in Verilog, follow these solutions and best practices:

1. Use wire for Continuous Assignments

Continuous assignments in Verilog must be made to wire types, not reg types.

Example:

module example1(output wire y, input wire a, b);
  assign y = a & b; // Correct: y is a wire
endmodule

2. Use reg for Procedural Assignments

Procedural assignments inside always blocks should be made to reg types.

Example:

module example2(output reg y, input wire a, b);
  always @ (a or b) begin
    y = a & b; // Correct: y is a reg
  end
endmodule

3. Avoid Mixing Continuous and Procedural Assignments

Do not mix continuous and procedural assignments for the same signal.

Incorrect Example:

module example3(output reg y, input wire a, b);
  assign y = a & b; // Error: y is a reg
  always @ (a or b) begin
    y = a | b; // Error: y is a reg
  end
endmodule

4. Declare Outputs Appropriately

Ensure that outputs driven by continuous assignments are declared as wire.

Example:

module example4(output wire y, input wire a, b);
  assign y = a & b; // Correct: y is a wire
endmodule

5. Use wire for Combinational Logic Outputs

For purely combinational logic, use wire for outputs.

Example:

module comb_logic(output wire y, input wire a, b);
  assign y = a & b; // Correct: y is a wire
endmodule

6. Correct Instantiation of Primitives

When instantiating Verilog primitives, ensure the port-mapped signals are of net type.

Example:

module example5(output wire y, input wire a, b);
  and (y, a, b); // Correct: y is a wire
endmodule

By following these practices, you can avoid the “concurrent assignment to a non-net is not permitted” error and ensure your Verilog code is syntactically correct and functionally robust.

Case Study

Case Study: Resolving ‘Concurrent Assignment to a Non-Net’ Error

Scenario

A developer encountered the error [VRFC 10-529] concurrent assignment to a non-net P is not permitted while working on a Verilog module for an array multiplier. The error occurred because the output P was declared as a reg type, which is not allowed for continuous assignments.

Initial Code

module Array_4x4_Multiplier (P, A, B);
    output reg [7:0] P;
    input [3:0] A, B;
    wire [6:1] S;
    wire [11:1] C;
    wire [15:0] W;

    and A1 (P[0], A[0], B[0]);
    // Additional logic
endmodule

Error Encountered

The error message indicated that P could not be assigned concurrently because it was declared as a reg. Continuous assignments in Verilog require the target to be a net type (e.g., wire).

Steps Taken to Resolve the Error

1. Identify the Issue: Recognized that P was declared as reg but used in a continuous assignment.
2. Change Declaration: Modified the declaration of P from reg to wire.
3. Update Code: Adjusted the code to reflect this change.

Updated Code

module Array_4x4_Multiplier (P, A, B);
    output wire [7:0] P;  // Changed from reg to wire
    input [3:0] A, B;
    wire [6:1] S;
    wire [11:1] C;
    wire [15:0] W;

    and A1 (P[0], A[0], B[0]);
    // Additional logic
endmodule

Outcome

After changing the declaration of P to wire, the error was resolved. The simulation ran successfully, and the expected output was obtained.

This case highlights the importance of using the correct data types for continuous assignments in Verilog.

The Error ‘Concurrent Assignment to a Non-NET’ in Verilog

The error ‘concurrent assignment to a non-net’ is not permitted occurs when attempting to assign a value to a signal that is declared as a reg type, which is not allowed for continuous assignments in Verilog.

To resolve this issue, the declaration of the signal must be changed from reg to wire, allowing it to be used in continuous assignments.

This highlights the importance of proper coding practices in Verilog, where using the correct data types for signals and nets is crucial for successful simulation and synthesis.